1. Field of the Invention
The present invention generally relates to a method for forming a semiconductor device, and more specifically, to a method for forming a semiconductor device having improved characteristics and reliability by forming a hard mask layer on a bit line to prevent degradation of characteristics of the device in a self-alignment contact process of a storage electrode.
2. Description of the Prior Art
In a semiconductor device, a lower conductive layer is interconnected to an upper conductive layer through a contact.
In a contact formation process of a semiconductor device which satisfies a design rule of less than 0.20 μm, since a masking process has a small overlap margin, a self aligned contact (“SAC”) process using a nitride film as an etching barrier is employed.
When the line width of a device is larger than 0.14 μm, a hole type SAC is used. When the line width of a device is smaller than 0.14 μm, a method for forming a contact wherein a line-type SAC process is combined with a CMP process is used due to small alignment margin.
FIGS. 1a through 1c are a plane view, a plane SEM photograph, and a cross-sectional SEM photograph taken along the line I—I of FIG. 1b, respectively, illustrating an example of a conventional semiconductor device.
Referring to FIG. 1a, a lower insulating layer (not shown) having a gate electrode (not shown) is formed on a semiconductor substrate (not shown).
Thereafter, the lower insulating layer is etched via a photolithography process using a landing plug contact mask to form a landing plug contact hole exposing an active region of the semiconductor substrate. A polysilicon layer (not shown) filling the landing plug contact hole is formed on the entire surface of the resulting structure, and then planarized to form a landing plug 11. The planarization process is performed using the hard mask layer on the gate electrode as etch barrier layer to form the landing plug 11 connected to the active region between the gate electrodes where a storage electrode or a bit line is to be contacted.
Thereafter, a first interlayer insulating film (not shown) is formed and then etched in a photolithography process using a bit line contact mask to form a bit line contact hole exposing the landing plug 11.
Thereafter, a bit line 13 connected to the landing plug 11 through the bit line contact hole is formed. The bit line 13 has a hard mask layer consisting of a nitride film thereon.
Next, a second interlayer insulating film 15 is formed on the entire surface of the resulting structure. The second interlayer insulating film 15 and the first interlayer insulating film are etched in a photolithography process using a storage electrode contact mask (not shown) to form a storage electrode contact hole 17 exposing the landing plug 11. A storage electrode contact plug connected to the landing plug 11 through the storage electrode contact hole 17 is then formed.
FIG. 1b is a SEM photograph illustrating a plane view of the storage electrode contact hole 17. “a” and “b” represent a bottom critical dimension CD and a top critical dimension CD of the storage electrode contact hole 17, respectively. As shown in FIG. 1b, “b” is larger than “a”.
FIG. 1c is a cross-sectional SEM photograph taken along the line I—I of FIG. 1b. As shown in FIG. 1c, “b” is larger than “a”.
FIGS. 2a through 2c are a plane diagram, a plane SEM photograph, a cross-sectional SEM photograph taken along the line II—II and III—III of FIG. 2a, respectively, illustrating another example of a conventional semiconductor device. FIGS. 2a through 2c illustrate a semiconductor device formed via the combination of a line-type SAC process and a CMP process to obtain sufficient alignment margin in contrary to FIG. 1a. 
Referring to FIG. 2a, a lower insulating layer (not shown) having a gate electrode (not shown) is formed on a semiconductor substrate (not shown).
Thereafter, the lower insulating layer is etched via a photolithography process using a landing plug contact mask to form a landing plug contact hole exposing an active region of the semiconductor substrate. A polysilicon layer (not shown) filling the landing plug contact hole is formed on the entire surface of the resulting structure, and then planarized to form a landing plug 21. The planarization process is performed using the hard mask layer on the gate electrode as etch barrier layer to form the landing plug 21 connected to the active region between the gate electrodes where a storage electrode or a bit line is to be contacted.
Thereafter, a first interlayer insulating film (not shown) is formed and then etched in a photolithography process using a bit line contact mask to form a bit line contact hole exposing the landing plug 21.
Thereafter, a bit line 23 connected to the landing plug 21 through the bit line contact hole is formed. The bit line 23 has a hard mask layer consisting of a nitride film thereon.
Next, a second interlayer insulating film 25 is formed on the entire surface of the resulting structure. The second interlayer insulating film 25 and the first interlayer insulating film are etched in a photolithography process using a line-type storage electrode contact mask (not shown), which is perpendicular to the bit line 23, to form a storage electrode contact hole 27 exposing the landing plug 21. The storage electrode contact hole 27 exposes a portion of the landing plug 21 at the crossing of the bit line 23, the line-type second interlayer insulating film 25 and the first interlayer insulating film.
Thereafter, a storage electrode contact plug connected to the landing plug 21 through the storage electrode contact hole 27 is formed.
FIG. 2b is a plane SEM photograph of FIG. 2a. In FIG. 2b, the contact holes are aligned on the contrary to FIG. 1b. “c” and “d” represent a bottom CD and a top CD of the storage electrode contact hole 17. As shown in FIG. 2b, “d” is larger than “c”.
FIG. 2c is a SEM photograph illustrating a hard mask layer e for a bit line and a bit line formed thereunder.
A gate electrode f, a landing plug g, a first interlayer insulating film h, and a second interlayer insulating film I are illustrated in FIG. 2d. However, a bit line is not shown.
FIGS. 3a through 3e are cross-sectional SEM photographs illustrating a conventional method for forming a semiconductor device.
Referring to FIG. 3a, a lower insulating layer (not shown) having a gate electrode (not shown) is formed on a semiconductor substrate (not shown).
Thereafter, the lower insulating layer is etched via a photolithography process using a landing plug contact mask to form a landing plug contact hole exposing an active region of the semiconductor substrate. A polysilicon layer (not shown) filling the landing plug contact hole is formed on the entire surface of the resulting structure, and then planarized to form a landing plug 31. The planarization process is performed using the hard mask layer on the gate electrode as etch barrier layer to form the landing plug 31 connected to the active region between the gate electrodes where a storage electrode or a bit line is to be contacted. The height of the hard mask layer is j.
Thereafter, a first interlayer insulating film (not shown) is formed and then etched in a photolithography process using a bit line contact mask to form a bit line contact hole exposing the landing plug 31.
Thereafter, a bit line 33 connected to the landing plug 31 through the bit line contact hole is formed. The bit line 33 has a hard mask layer consisting of a nitride film thereon.
Referring to FIG. 3b, a nitride film spacer is formed on a sidewall of the bit line 33. The nitride film spacer is formed by depositing a nitride film having a thickness ranging from 250 to 350 Å on the entire surface of the resulting structure and then anisotropically etching the nitride film. In the etching process, the nitride film is over-etched by 500 to 600 Å, and the thickness of the hard mask layer on the bit line 33 is decreased from j to k due to the over-etching.
Referring to FIG. 3c, a second interlayer insulating film (not shown) is formed on the entire surface of the resulting structure. The second interlayer insulating film and the first interlayer insulating film are etched in a photolithography process using a line-type storage electrode contact mask (not shown), which is perpendicular to the bit line 33, to form a storage electrode contact hole (not shown) exposing the landing plug 31. The storage electrode contact hole exposes a portion of the landing plug 31 at the crossing of the bit line 33, the line-type second interlayer insulating film and the first interlayer insulating film.
Thereafter, a polysilicon layer (not shown) filling the storage electrode contact hole is formed on the entire surface of the resulting structure, and then planarized to form a storage electrode contact plug 35 connected to the landing plug 31 through the storage electrode contact hole.
The planarization process is a CMP (Chemical Mechanical Polishing) process. “A” denotes a planarized state. Since the hard mask layer on the bit line 33 is etched in the CMP process, the thickness of the hard mask layer is decreased from k to l. As a result, an insulating characteristic of the bit line 33 is degraded.
Referring to 3d, a storage electrode 37 connected to the storage electrode contact plug 35 is formed in a subsequent process. Since the interval m between the bit line 33 and the storage electrode 37 becomes smaller, the margin for maintaining the insulating characteristic is decreased.
FIG. 3e illustrates a contact hole formed by performing a wet-etching process and subsequent processes to enlarge bottom CD of the contact hole as shown in FIGS. 1b and 2b. A groove n is formed at the lower portion of the bit line by the wet-etching process, and the material used for the formation of the storage electrode contact plug 35 is filled therein, which degrades the characteristics of a device.
As described above, in the conventional method for forming a semiconductor device, the hard mask layer of the bit line is damaged due to an excessive CMP performed to isolate contact plugs in the CMP process for forming a line-type contact plug, thereby degrading characteristics of a device.
Specifically, since a pattern density or a polishing degree in each wafer is not uniform, when the storage electrode contact plugs are isolated on the entire surface of a wafer, bit lines in certain regions are exposed. When a capacitor is formed in a subsequent process, short between the capacitor and the bit line occurs.
In the SAC process performed in the second example, the possibility of the SAC defects, which are connection defects between conductive layers, generated due to the damages in nitride films are much larger than that of the first example. When the thickness of the nitride film is increased to overcome the problem, voids can be generated, thereby degrading characteristics of a device.